DataPig-Adapter: A fanout board to test LHCb UT’s Flexes

An adapter with more than 2000€ worth of connectors might seem odd. Where’s the trick then?

Board-Released
Top view with two BDR connectors (BW up to 20GHz), resistors and 8x 40POS Headers

LHCb is one of 4 main experiments built around the LHC accelerator at CERN; this winter it will be shut down to start an important upgrade, and with that, new subdetectors will be installed, leading to this little adapter board: testing time!

Board-Released-2
Bottom side view with the MegArray connector in white

DataPig-Adapter is just a name to highlight what this board is for: adapting the testing electronics to the two flexible cables that are going to be used in the Upstream Tracker of LHCb, namely “Dataflex” and “Pigtail”.

Once connected, the testing electronics, a TDR (Time Domain Reflectometer) and a cable tester, will make sure that all the lines on our DUTs are ok and will validate (or mark as FAIL) the flexible PCB towards its end destination at CERN.

This is why you do find some cheap connectors near 2000€  top of the notch high bandwidth ones. Headers are there to test connectivity and resistance: we need to make sure that every line reaches the front end electronics and the backend readout, with the added information of understanding how they were etched during production (too much or spot on). Then, when we are sure everything is there, we can start injecting TDR pulses to probe 12 critical lines, and those are the ones routed to the two Samtec pile-of-cash SMA connectors.

BDR connector assembled with 24 SMA cables at CERN
Example of a BDRA (Connector + Assembled SMA cables) mounted on a high-speed PCB [CERN]
The layout is pretty simple. 6 copper layers, all 35um thick, connecting a 400 pin BGA from Amphenol (MegArray 400) to 8x 0.1″ 40POS headers and two 24pos BDR connectors from Samtec.

MID3
Inner Layer copper, all signal lines are routed as differential pairs

Last but not least, there are also 5 High-Frequency resistors here and there to have some reference lines on the board when running the TDR or VNA analysis.

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