A flex thin 5 layer board with lots of caps and wire-bonding pads: LHCb UT’s front end PCB prototype.
Research means to try new things, let it be in simulation or real life. For LHCb, we chose the latter.
Naturally, there’s a reason behind prototyping on real hardware instead of a simulation, but I’m not going to dive deep into it in this article: it has to do with LHCb UT (Upstream Tracker) own time constraints and planned tests scheduled in the near future.
This prototype comes as the seventh iteration of what we internally (LHCb Collaboration) call DELTA HYBRID, the front end board prototype designed to test SALT128 ASICs (Integrated circuits especially developed for this particle detector, the Upstream Tracker). (See SALT128 datasheet and block diagram on our CERN wiki page).
Due to the amount of copper and ceramic (capacitors) on DELTA, it is clear that we’re looking at a design that cannot be installed inside LHCb, mainly due to the fact that so much material will STOP particles instead of letting them pass through all detectors, being identified, tagged and studied. (See Radiation Length on Wikipedia).
Thus, again, this PCB is considered a testing board, very similar to the final front end board, but still, a prototype in need to be improved.
The PCB is designed to act as a power delivery and decoupling board, plus clock (40MHz circa.) and slow control distribution (I2C, RESET) in a Fly-By topology.
Each ASIC transmits data at 160Mbps on 4x SLVS channels (actually, we can scale it down, meaning we can transmit data on 3 lines or, on another test board, on 5).
The clock is received from an SLVS clock generator that matches LHC own clock (40 MHz ca. defined by the rate at which collisions happen inside the detector, roughly one bunch of particles hitting another each 25ns).
In the middle of the PCB you’ll notice a thermistor, this is used to monitor the PCB temperature during data taking and testing, a critical information to make sure we’re not running too hot (temperature distribution with 4 active IC loads simulated in ANSYS).
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